/* File: startup_ARMCM0.S
 * Purpose: startup file for Cortex-M0 devices. Should use with
 *   GCC for ARM Embedded Processors
 * Version: V2.01
 * Date: 12 June 2014
 *
 */
/* Copyright (c) 2011 - 2014 ARM LIMITED

   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
   - Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   - Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   - Neither the name of ARM nor the names of its contributors may be used
     to endorse or promote products derived from this software without
     specific prior written permission.
   *
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
   ---------------------------------------------------------------------------*/

#include "user_custom.h"

	.syntax	unified
	.arch	armv6-m

	.section .stack
	.align	3
#ifdef __STACK_SIZE
	.equ	Stack_Size, __STACK_SIZE
#else
	.equ	Stack_Size, 0x00000400
#endif
	.globl	__StackTop
	.globl	__StackLimit
__StackLimit:
	.space	Stack_Size
	.size	__StackLimit, . - __StackLimit
__StackTop:
	.size	__StackTop, . - __StackTop

	.section .heap
	.align	3
#ifdef __HEAP_SIZE
	.equ	Heap_Size, __HEAP_SIZE
#else
	.equ	Heap_Size, 0x00000040
#endif
	.globl	__HeapBase
	.globl	__HeapLimit
__HeapBase:
	.if	Heap_Size
	.space	Heap_Size
	.endif
	.size	__HeapBase, . - __HeapBase
__HeapLimit:
	.size	__HeapLimit, . - __HeapLimit

	.section .vectors
	.align 2
	.globl	__Vectors
__Vectors_0:
	ldr		r0, =Reset_Handler
	bx		r0
__Vectors:
	.long	__StackTop            /* Top of Stack */
	.long	Reset_Handler         /* Reset Handler */
	.long	NMI_Handler           /* NMI Handler */
	.long	HardFault_Handler     /* Hard Fault Handler */
	.long	0                     /* Reserved */
	.long	0                     /* Reserved */
	.long	0                     /* Reserved */
	.long	0                     /* Reserved */
	.long	0                     /* Reserved */
	.long	0                     /* Reserved */
	.long	0                     /* Reserved */
	.long	SVC_Handler           /* SVCall Handler */
	.long	0                     /* Reserved */
	.long	0                     /* Reserved */
	.long	PendSV_Handler        /* PendSV Handler */
	.long	SysTick_Handler       /* SysTick Handler */

	/* External interrupts */
	.long	vInterruptHdmacCh0      /*  0: DMAC ADC data transfer     */
	.long	vInterruptHdmacCh1      /*  1: DMAC UART receive          */
	.long	vInterruptHdmacCh2      /*  2: DMAC UART transmission     */
	.long	vInterruptHdmacCh3      /*  3: DMAC QSPI transmission     */
	.long	vInterruptHdmacCh4      /*  4: DMAC QSPI receive          */
	.long	vInterruptUartRx        /*  5: UART receive               */
	.long	vInterruptUartTx        /*  6: UART transmission          */
	.long	vInterruptSpi           /*  7: QSPI                       */
	.long	vInterruptCalendar      /*  8: Calendar alarm             */
	.long	vInterruptTimer32       /*  9: 32bit timer under flow     */
	.long	vInterruptAdc           /* 10: ADC interrupt              */
	.long	vInterruptI2c           /* 11: I2C.smb_int                */
	.long	vInterruptWatchdog      /* 12: Watch dog                  */
	.long	vInterruptTempSensorIf  /* 13: Temperature                */
	.long	0                       /* 14: Reserved                   */
	.long	PMU_IRQHandler          /* 15: PMU                        */
	.long	TIMER_0_IRQHandler      /* 16: Timer interrupt[0] from Per*/
	.long	TIMER_1_IRQHandler      /* 17: Timer interrupt[0] from Per*/
	.long	TIMER_2_IRQHandler      /* 18: Timer interrupt[0] from Per*/
	.long	USB20_IRQHandler        /* 19: INT_USB20 from JMLEXS9M    */
	/* ### DELETE_SECURE */
	#if 1
	.long	NETSEC_A_IRQHandler 	/* 20: INT_NETSEC_A from JMLEXS9M */
	.long	NETSEC_B_IRQHandler 	/* 21: INT_NETSEC_B from JMLEXS9M */
	#else
	/* ### DELETE_SECURE */
	.long	0                       /* 20: Reserved                   */
	.long	0                       /* 21: Reserved                   */
	/* ### DELETE_SECURE */
	#endif
	/* ### DELETE_SECURE */
	.long	vInterruptCtc           /* 22: Cycle time counter MIME int*/
	.long	0                       /* 23: Reserved                   */
	.long	0                       /* 24: Reserved                   */
	.long	0                       /* 25: Reserved                   */
	.long	0                       /* 26: Reserved                   */
	.long	vInterruptIpcuCh0       /* 27: IPCU [0]                   */
	.long	vInterruptIpcuCh1       /* 28: IPCU [1]                   */
	.long	vInterruptIpcuCh2       /* 29: IPCU [2]                   */
	.long	vInterruptIpcuCh3       /* 30: IPCU [3]                   */
	.long	vInterruptGpio          /* 31: GPIO Int. from External In */

	.size	__Vectors, . - __Vectors

	.text
	.thumb
	.thumb_func
	.align	1
	.globl	Reset_Handler
	.type	Reset_Handler, %function
Reset_Handler:
#ifdef BOOT_LED
	/* Boot start : LED10(P24) On */
	ldr	r0, =0x4DFFB004
	ldr	r1, =0xFFFF0010
	str	r1, [r0]
#endif	/* BOOT_LED */
	ldr	r0, =0
	msr	control, r0
#ifdef __STARTUP_SET_SP
	ldr	r0, =__Vectors
	ldr	r1, [r0]
	mov	sp, r1
#endif	/* __STARTUP_SET_SP */

#ifdef __STARTUP_INT_VECT
	ldr	r0, =__Vectors
	ldr	r1, =(0x3FFE0000 + 12)
	movs	r2, (16 + 32)
1:
	ldr	r3, [r0]
	adds	r0, 4
	str	r3, [r1]
	adds	r1, 16
	subs	r2, 1
	bne		1b
#endif

#ifdef __STARTUP_HW
	bl	vStartupHW
#endif	/* __STARTUP_HW */

/*  Firstly it copies data from read only memory to RAM. There are two schemes
 *  to copy. One can copy more than one sections. Another can only copy
 *  one section.  The former scheme needs more instructions and read-only
 *  data to implement than the latter.
 *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */

#ifdef __STARTUP_COPY_MULTIPLE
/*  Multiple sections scheme.
 *
 *  Between symbol address __copy_table_start__ and __copy_table_end__,
 *  there are array of triplets, each of which specify:
 *    offset 0: LMA of start of a section to copy from
 *    offset 4: VMA of start of a section to copy to
 *    offset 8: size of the section to copy. Must be multiply of 4
 *
 *  All addresses must be aligned to 4 bytes boundary.
 */
	ldr	r4, =__copy_table_start__
	ldr	r5, =__copy_table_end__

.L_loop0:
	cmp	r4, r5
	bge	.L_loop0_done
	ldr	r1, [r4]
	ldr	r2, [r4, #4]
	ldr	r3, [r4, #8]

.L_loop0_0:
	subs	r3, #4
	blt	.L_loop0_0_done
	ldr	r0, [r1, r3]
	str	r0, [r2, r3]
	b	.L_loop0_0

.L_loop0_0_done:
	adds	r4, #12
	b	.L_loop0

.L_loop0_done:
#else
/*  Single section scheme.
 *
 *  The ranges of copy from/to are specified by following symbols
 *    __etext: LMA of start of the section to copy from. Usually end of text
 *    __data_start__: VMA of start of the section to copy to
 *    __data_end__: VMA of end of the section to copy to
 *
 *  All addresses must be aligned to 4 bytes boundary.
 */
	ldr	r1, =__etext
	ldr	r2, =__data_start__
	ldr	r3, =__data_end__

	subs	r3, r2
	ble	.L_loop1_done

.L_loop1:
	subs	r3, #4
	ldr	r0, [r1,r3]
	str	r0, [r2,r3]
	bgt	.L_loop1

.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */

/*  This part of work usually is done in C library startup code. Otherwise,
 *  define this macro to enable it in this startup.
 *
 *  There are two schemes too. One can clear multiple BSS sections. Another
 *  can only clear one section. The former is more size expensive than the
 *  latter.
 *
 *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
 *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
 */
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/*  Multiple sections scheme.
 *
 *  Between symbol address __copy_table_start__ and __copy_table_end__,
 *  there are array of tuples specifying:
 *    offset 0: Start of a BSS section
 *    offset 4: Size of this BSS section. Must be multiply of 4
 */
	ldr	r3, =__zero_table_start__
	ldr	r4, =__zero_table_end__

.L_loop2:
	cmp	r3, r4
	bge	.L_loop2_done
	ldr	r1, [r3]
	ldr	r2, [r3, #4]
	movs	r0, 0

.L_loop2_0:
	subs	r2, #4
	blt	.L_loop2_0_done
	str	r0, [r1, r2]
	b	.L_loop2_0
.L_loop2_0_done:

	adds	r3, #8
	b	.L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/*  Single BSS section scheme.
 *
 *  The BSS section is specified by following symbols
 *    __bss_start__: start of the BSS section.
 *    __bss_end__: end of the BSS section.
 *
 *  Both addresses must be aligned to 4 bytes boundary.
 */
	ldr	r1, =__bss_start__
	ldr	r2, =__bss_end__

	movs	r0, 0

	subs	r2, r1
	ble	.L_loop3_done

.L_loop3:
	subs	r2, #4
	str	r0, [r1, r2]
	bgt	.L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */

#ifndef __NO_SYSTEM_INIT
	bl	SystemInit
#endif

#ifndef __START
#define __START _start
#endif
	bl	__START

	.pool
	.size	Reset_Handler, . - Reset_Handler

	.align	1
	.thumb_func
	.weak	Default_Handler
	.type	Default_Handler, %function
Default_Handler:
	b	.
	.size	Default_Handler, . - Default_Handler

/*    Macro to define default handlers. Default handler
 *    will be weak symbol and just dead loops. They can be
 *    overwritten by other handlers */
	.macro	def_irq_handler	handler_name
	.weak	\handler_name
	.set	\handler_name, Default_Handler
	.endm

	def_irq_handler	NMI_Handler
	def_irq_handler	HardFault_Handler
	def_irq_handler	SVC_Handler
	def_irq_handler	PendSV_Handler
	def_irq_handler	SysTick_Handler

	def_irq_handler	DMAC_ADC_IRQHandler
	def_irq_handler	DMAC_UART_R_IRQHandler
	def_irq_handler	DMAC_UART_T_IRQHandler
	def_irq_handler	DMAC_QSPI_T_IRQHandler
	def_irq_handler	DMAC_QSPI_R_IRQHandler
	def_irq_handler	UART_R_IRQHandler
	def_irq_handler	UART_T_IRQHandler
	def_irq_handler	QSPI_IRQHandler
	def_irq_handler	CALENDAR_IRQHandler
	def_irq_handler	TIMER32_IRQHandler
	def_irq_handler	ADC_IRQHandler
	def_irq_handler	I2C_IRQHandler
	def_irq_handler	WATCHDOG_IRQHandler
	def_irq_handler	TEMPERATURE_IRQHandler
	def_irq_handler	PMU_IRQHandler
	def_irq_handler	TIMER_0_IRQHandler
	def_irq_handler	TIMER_1_IRQHandler
	def_irq_handler	TIMER_2_IRQHandler
	def_irq_handler	USB20_IRQHandler
	/* ### DELETE_SECURE */
	def_irq_handler NETSEC_A_IRQHandler
	def_irq_handler NETSEC_B_IRQHandler
	/* ### DELETE_SECURE */
	def_irq_handler	IPCU_0_IRQHandler
	def_irq_handler	IPCU_1_IRQHandler
	def_irq_handler	IPCU_2_IRQHandler
	def_irq_handler	IPCU_3_IRQHandler
	def_irq_handler	GPIO_IRQHandler

	.end
